(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming high quality shallow trench isolation (STI) in the fabrication of integrated circuits.
(2) Description of the Prior Art
Shallow trench isolation (STI) is often used in the fabrication of integrated circuits to separate active areas. After the trench has been filled with an oxide, nitride blocks resting on pad oxide layers over active areas typically serve as stopping layers for the chemical mechanical polishing (CMP) of the oxide to leave the oxide only in the trench. The removal of the nitride blocks later by wet chemical cleans, however, induces divots of varying depths to develop at the edges of the STI near the silicon active region.
FIG. 1 shows the STI region 20 formed in the semiconductor substrate 10. Pad oxide layer 12 and nitride blocking layer 14 are shown. The figure shows a stage near the end point of the CMP step. Next, wet nitride removal steps remove the nitride and a heavy oxide dip removes the pad oxide. Consequently, divots 22 are formed at the edges of the STI, as shown in FIG. 2. These divots are potential hidden nodes for suicides, and they are sometimes responsible for high field edge leakage if the source/drain junctions at these edges are shallow. That is, silicide will form within the divot and can grow steeply downwards at 28. It the elongated silicide is below the depth of the junctions 24, formed at a later step, there will be high leakage and possibly a short. The segregation of dopants, especially boron, at STI field edges reduces junction depth. After the junctions are silicided 26, the silicide formed by metal remaining at the STI divots 22, if they are show steep growth downwards, can become shorting routes 30 to the substrate. The consequence of this is large leakage currents from the source/drain junctions to the well or substrate.
A number of patents have addressed the formation of shallow trenches. U.S. Pat. No. 5,807,784 to Kim teaches an ion implant for oxidation within a trench, then oxide fill and CMP. U.S. Pat. No. 5,646,063 to Mehta et al shows an STI process with CMP. U.S. Pat. No. 5,801,082 to Tseng discloses a spin-on-glass coating and etchback for corner rounding of an STI. U.S. Pat. No. 6,001,708 to Liu et al discloses a nitride cap layer over an oxide trench fill to prevent dishing during CMP. Co-pending U.S. patent application Ser. No. 09/405,061 (CS-98-162) to L. C. Wee et al filed on Sep. 27, 1999 prevents the formation of oxide divots by forming oxide spacers on the nitride blocks and using a silicon soft sputter etch. Co-pending U.S. patent application Ser. No. 09/439,358 (CS-99-148) to H. T. Kim et al filed on Nov. 15, 1999 prevents the formation of oxide divots by depositing a polysilicon layer under the nitride blocks and oxidizing the polysilicon to protect the edges of the STI. All of these aforementioned methods use nitride blocks.
Accordingly, the primary object of the invention is to provide a process for forming shallow trench isolation in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated.
Still another object is to provide a process for forming shallow trench isolation without the use of a nitride blocking layer.
Yet another object is to provide a process for forming shallow trench isolation without the use of a nitride blocking layer wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated.
Yet another object of the invention is to provide a process for forming shallow trench isolation without the use of a nitride blocking layer wherein a nitrogen ion implant is used to control the CMP process.
A still further object of the invention is to provide a process for forming shallow trench isolation without the use of a nitride blocking layer wherein a nitrogen ion implant is used to control the CMP process thereby reducing or eliminating oxide divots at the edge of the isolation and active regions.
In accordance with the objects of the invention, a method for forming shallow trench isolation wherein oxide divots at the edge of the isolation and active regions are reduced or eliminated is achieved. A trench is etched into a semiconductor substrate. An oxide layer is deposited overlying the semiconductor substrate and filling the trench. Nitrogen atoms are implanted into the oxide layer overlying the trench. The substrate is annealed whereby a layer of nitrogen-rich oxide is formed at the surface of the oxide layer overlying the trench. The oxide layer is planarized to the semiconductor substrate wherein the nitrogen-rich oxide layer is planarized more slowly than the oxide layer resulting in a portion of the oxide layer remaining overlying the trench after the oxide layer overlying the semiconductor substrate has been removed, completely or mostly removed, wherein the portion of the oxide layer remaining over the STI provides a smooth transition between the shallow trench isolation and the active areas completing the formation of shallow trench isolation in the fabrication of an integrated circuit device.